1. Technical Field of the Invention
The present invention relates to semiconductor devices and methods for manufacturing the same, and more particularly to a semiconductor device having an interlayer dielectric layer in which the dielectric layer is well embedded between wiring layers even when the gap between the wiring layers is particularly narrow, and a method for manufacturing the same.
2. Background Technology and Problems to be Solved By the Invention
In semiconductor devices such as LSIs, the width of wiring layers has become small and the gap between the wiring layers has also become narrow due to further device miniaturization, higher densification, and greater number of multiple layers. For example, in the 0.13 μm generation design rule, the minimum line width of a metal wiring layer is 0.2 μm, and the minimum gap is 0.22 μm. When silicon oxide is embedded by a CVD method in such a narrow gap between the wiring layers, voids may be generated in the embedded silicon oxide layer because the gap between the wiring layers is too narrow, resulting in an embedding failure.
Coated silicon oxide called SOG (Spin On Glass) is provided by spin-coating a wafer with a dielectric film material dissolved in an organic solvent, and then hardening the layer by a heat treatment. Such a SOG is excellent in its embedding property due to its high fluidity. However, when the SOG is subject to a heat treatment for thermosetting, which is called “curing”, the SOG layer shrinks as the organic solvent evaporates.
The inventors of the present invention have confirmed that, when a SOG layer is used as an interlayer dielectric layer between wiring layers that are formed according to, for example, the 0.13 μm generation design rule, a shrinkage occurs in the SOG layer, and causes a compression force against the wiring layers in their thickness direction, which would likely deform metal wiring layers such as aluminum layers in particular. When wiring layers are deformed, the wiring reliability and migration resistivity may lower. In addition, deformations in wiring layers would occur particularly in wiring layers having patterns that are isolated from others.
It is an object of the present invention to provide a semiconductor device having an interlayer dielectric layer with an excellent embedding property for gaps between adjacent wiring layers even when they are formed in accordance with, for example, a sub 0.13 μm generation design rule, and a method for manufacturing the same.